One technique to allow communication between two electronic devices such as integrated circuit chips is to use electrically conductive connections between the electronic devices. Typically, these electrically conductive connections are on a PC board or the like. However, a drawback of such electrically conductive connections is the limited amount of information that can be transmitted between devices. This problem and others associated with inter-device communication are becoming more significant as electronic devices become more complex. Moreover, new ways of assembling groups of two or more electronic devices may allow for better inter-device communication. However, it is difficult to fully take advantage of the new ways of assembling groups of devices.
For example, multi-chip packaging is used to assemble two or more electronic devices, such as integrated circuit chips. Multi-chip packaging allows for communication by a technique referred to as “proximity communication”, which uses capacitive coupling to provide communications between chips which are oriented face-to-face. This capacitive coupling can provide signal densities two orders of magnitude denser than traditional off-chip communication using wire-bonding or traditional ball-bonding, while the circuits and coupling structures remain fully-compatible with standard CMOS foundries. To communicate off-chip through capacitive coupling, on-chip circuits drive high-impedance, capacitive transmitter pads.
While proximity communication provides off-chip signaling bandwidth that scales with chip feature size, it also introduces topological constraints. The active sides of chips typically need to face each other in a precise alignment, so that corresponding transmitter and receiver pads on opposing chips align both laterally and vertically. Achieving and maintaining chip alignment for proximity communication is challenging.
Typically, the chips are assembled with a “pick-and-place” technique that is cost efficient. However, the pick-and-place (as well as other known cost effective techniques) can only assembly the chips to within several mils of tolerance. Furthermore, commercial package materials also have flatness variations. Thus, techniques that may provide high-bandwidth inter-chip communication are difficult, if not impossible to achieve, given the tolerance of typical multi-chip assembly techniques.
Therefore, improved techniques for assembling electronic devices in such as way that will allow communication of large amounts of information between the electronic devices, such as integrated circuit chips is desired.
The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.